Performance evaluation over HW/SW co-design SoC memory transfers for a CNN accelerator

FPGA devices have demonstrated to be one of the most popular prototyping solutions. N anoelectronics is one of the fields that can prototype its architectures in these devices. Many FPGA vendors have recently included embedded processors in their devices, such as Xilinx with ARM -Cortex A cores, together with programmable logic cells. These devices are known as Programmable System on Chip (PSoC). Their ARM cores (embedded in the processing system or PS) communicates with the programmable logic cells (PL) using ARM-standard interface buses. ARM proposed the Advanced Microcontroller Bus Architecture (AMBA) as an open-standard. Its third generation included the Advanced eXtensible Interface (AXI) to reach higher performances. In this paper we analyse the performance of exhaustive data transfers between PS and PL for a Xilinx Zynq FPGA in a co-design real scenario for Convolutional Neural Networks (CNN) accelerator. This CNN accelerator processes, in dedicated hardware, a stream of visual information from a neuromorphic visual sensor for classification. In the PS side, a Linux operating system is running, which recollects visual events from the neuromorphic sensor into a normalized frame, and then it transfers these frames to the CNN accelerator of multi-layered CNNs; and read results, using an AXI-DMA bus in a per-layer way. As these kind of accelerators try to process information as quick as possible, data bandwidth becomes critical. Maintaining a good balanced data throughput rate requires some considerations, such as data partitioning techniques to balance RX and TX transfers, or different transfer management techniques: polling versus dedicated interrupt-based kernel-level driver. For longer enough packets, the kernel-level driver solution improves global computation timings in a CNN classification example. Kernel-level driver ensures safer solutions and enables OS tasks, scheduling for better computation distribution.