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A Novel Selective Harmonic Mitigation PWM Technique With THD Minimization Using Second-Order Sliding Modes

Abstract

This article proposes a novel selective harmonic mitigation technique based on higher order slidingmode control. The method aims to reduce total harmonic distortion (THD) while mitigating multiple harmonics as necessary according to existing standards, such as IEEE 519-2022. Unlike selective harmonic elimination (SHE), which can only eliminate a fixed number of harmonics, the proposed method can accommodate (m - 1) or more harmonics corresponding to m switching angles per quarter wave. The proposed methodology constrains the number of switching angles similar to SHE but achieves a lower THD and meets the IEEE 519-2022 requirements by alleviating multiple harmonics simultaneously. Complete details of the proposed algorithm are provided for a general case with m switching angles. Simulations in MATLAB/Simulink and experiments on a field-programmable gate array (FPGA) prototype validate the technique for m = 5 switching angles. Various test cases demonstrate the ability to mitigate specific harmonics while minimizing THD. Notably, the proposed SHM technique could mitigate up to four additional lower order harmonics above SHE with just five switching angles and two levels.

article Article
date_range 2025
language English
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Featured Keywords

Harmonic analysis
Switches
Task analysis
Standards
Modulation
Mathematical models
Logic gates
Low switching frequency
pulse width modulation (PWM)
selective harmonic mitigation (SHM)
total harmonic distortion (THD)
two-level inverter
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